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NT256D72S89AKGU
256MB : 32M x 72
Low Profile Registered DDR SDRAM DIMM
184pin Low Profile Registered DDR SDRAM MODULE Based on 32Mx8 DDR SDRAM Features
* 32Mx72 Low Profile Registered DDR DIMM based on 32Mx8 DDR SDRAM * JEDEC Standard 184-pin Dual In-Line Memory Module * Error Check Correction (ECC) Support * Phase-lock loop (PLL) clock driver to reduce loading * Registered inputs with one-clock delay
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* Performance: PC1600 Speed Sort DIMM CAS Latency f CK Clock Frequency t CK Clock Cycle f DQ DQ Burst Frequency
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* Data is read or written on both clock edges * Bi-directional data strobe with one clock cycle preamble and one-half clock post-amble * Address and control signals are fully synchronous to positive clock edge * Programmable Operation: - Device CAS Latency: 2, 2.5
PC2100 -75B 3.5 133 7.5 266 -7K 3 133 7.5 266 MHz ns MHz Unit
- Burst Type: Sequential or Interleave - Burst Length: 2, 4, 8 - Operation: Burst Read and Write
-8B 3 100 10 200
* Auto Refresh (CBR) and Self Refresh Modes * 13/10/1 Addressing (row/column/bank) * Serial Presence Detect * Gold contacts
* Automatic and controlled precharge commands * 7.8 s Max. Average Periodic Refresh Interval
* Intended for 100 MHz and 133 MHz applications * Inputs and outputs are SSTL-2 compatible * VDD = 2.5Volt 0.2, VDDQ = 2.5Volt 0.2 * SDRAMs have 4 internal banks for concurrent operation * Differential clock inputs
*
* SDRAMs in 66-pin TSOP Type II Package
One clock cycle added for registered DIMMs to account for input register.
Description
NT256D72S89AKGU is a Low Profile Registered 184-Pin 1U Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM), organized as a one-bank 32Mx72 high-speed memory array. The module uses nine 32Mx8 DDR SDRAMs in 400 mil TSOP II packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs.
common design files minimizes electrical variation between suppliers. All NANYA DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint.
The DIMM is intended for use in applications operating up to 133 MHz clock speeds and achieves high-speed data transfer rates of up to 266 MHz. Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
Ordering Information
Part Number Speed 143MHz (7ns @ CL = 2.5) DDR266A 133MHz (7.5ns @ CL= 2) 133MHz (7.5ns @ CL= 2.5) NT256D72S89AKGU-75B 100MHz (10ns @ CL = 2) 125MHz (8ns @ CL = 2.5) NT256D72S89AKGU-8B 100MHz (10ns @ CL = 2) DDR200 PC1600 DDR266B PC2100 32Mx72 Gold PC2100 Organization Leads Power
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NT256D72S89AKGU-7K
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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(c) NANYA TECHNOLOGY CORP.
NT256D72S89AKGU
256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM
Pin Description
CK0, CK0 CKE0 RAS CAS WE S0 A0-A9, A11, A12 A10/AP BA0, BA1 RESET VREF VDDID Differential Clock Inputs Clock Enable Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge SDRAM Bank Address Inputs Reset pin Ref. Voltage for SSTL_2 inputs VDD Identification flag. DQ0-DQ63 CB0-CB7 DQS0-DQS8 DM0-DM8 VDD VDDQ VSS NC SCL SDA SA0-2 VDDSPD Data input/output Check Bit Data Input/Output Bidirectional data strobes Input Data Mask Power (2.5V) Supply voltage for DQs (2.5V) Ground No Connect Serial Presence Detect Clock Input Serial Presence Detect Data input/output Serial Presence Detect Address Inputs Serial EEPROM positive power supply (2.5V)
Pinout
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Front VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC RESET VSS DQ8 DQ9 DQS1 VDDQ NC NC VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 53 54 55 56 57 58 59 60 61 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Front A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 KEY DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front VDDQ WE DQ41 CAS VSS DQS5 DQ42 DQ43 VDD NC DQ48 DQ49 VSS NC NC VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Back VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 NC VDDQ NC DQ20 A12 VSS DQ21 A11 DQS11 VDD DQ22 A8 DQ23 145 146 147 148 149 150 151 152 153 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Back VSS A6 DQ28 DQ29 VDDQ DM3 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 CK0 VSS DM8 A10 CB6 VDDQ CB7 KEY VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Back RAS DQ45 VDDQ S0 NC DM5 VSS DQ46 DQ47 NC VDDQ DQ52 DQ53 NC VDD DM6 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
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NT256D72S89AKGU
256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM
Input/Output Functional Description
Symbol CK0 CK0 Type (SSTL) Polarity Function The positive line of the differential pair of system clock inputs which drives the input to Positive the on-DIMM PLL. All the DDR SDRAM address and control inputs are sampled on the Edge rising edge of their associated clocks. Negative The negative line of the differential pair of system clock inputs which drives the input to Edge the on-DIMM PLL. Active High Active Low Active Low Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to be executed by the SDRAM. Reference voltage for SSTL-2 inputs Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA10) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. Data and Check Bit input/output pins operate in the same manner as on conventional DRAMs. Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM configurations. Power and ground for the DDR SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Active High Active Low Supply Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pullup. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pullup. Serial EEPROM positive power supply. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules.
(SSTL)
CKE0
(SSTL)
S0 RAS, CAS, WE VREF VDDQ BA0, BA1
(SSTL)
(SSTL) Supply Supply (SSTL)
A0 - A9 A10/AP A11, A12
(SSTL)
-
DQ0 - DQ63 DQ0 - DQ63 CB0 - CB7 VDD, VSS
(SSTL) (SSTL) Supply
Active High
DQS0 - DQS8
(SSTL)
DM0 - DM8
Input
RESET SA0 - SA2 SDA SCL V DDSPD
(LVC-MOS)
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NT256D72S89AKGU
256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM
Functional Block Diagram (1 Bank, 32Mx8 DDR SDRAMs)
RS0 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DM8/DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7/DQS16 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6/DQS15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5/DQS14 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DQS4 DM4/DQS13 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS
D0
D4
D1
D5
D2
D6
D3
D7
D8
S0 BA0-BA1 A0-A12 RAS CAS CKE0 WE PCK PCK Notes :
R E G I S T E R
RS0 RBA0-RBA1 RA0-RA12 RRAS RCAS RCKE0 RWE RESET
CS : SDRAMs D0-D8 BA0-BA1 : SDRAMs D0-D8 A0-A12 : SDRAMs D0-D8 RAS : SDRAMs D0-D8 CAS : SDRAMs D0-D8 CKE : SDRAMs D0-D8 WE : SDRAMs D0-D8
VDDSPD VDDQ VDD VREF VSS VDDID
Serial PD D0-D8 D0-D8 D0-D8 D0-D8 Strap : see Note 4
Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA
1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/CS relationships are maintained as shown. 3. DQ/DQS resistors are 22 Ohms. 4. VDDID strap connections (for memory device VDD,VDDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD is not equal to VDDQ 5. Address and control resistors are 22 Ohms.
CK0, CK0 --------- PLL* * Wire per Clock Loading Table/Wiring Diagrams
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NT256D72S89AKGU
256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM
Serial Presence Detect -- Part 1 of 2
32Mx72 1 BANK REGISTERED DDR SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD SPD Entry Value Byte Description Number of Serial PD Bytes Written during Production Total Number of Bytes in Serial PD device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of DIMM Bank Data Width of Assembly Data Width of Assembly (cont') Voltage Interface Level of this Assembly DDR SDRAM Device Cycle Time at CL=2.5 DDR SDRAM Device Access Time from Clock at CL=2.5 DIMM Configuration Type Refresh Rate/Type Primary DDR SDRAM Width Error Checking DDR SDRAM Device Width DDR SDRAM Device Attr: Min CLk Delay, Random Col Access DDR SDRAM Device Attributes: Burst Length Supported DDR SDRAM Device Attributes: Number of Device Banks DDR SDRAM Device Attributes: CAS Latencies Supported DDR SDRAM Device Attributes: CS Latency DDR SDRAM Device Attributes: WE Latency DDR SDRAM Device Attributes: DDR SDRAM Device Attributes: General Minimum Clock Cycle at CL=2 Maximum Data Access Time from Clock at CL=2 Minimum Clock Cycle Time at CL=1 Maximum Data Access Time from Clock at CL=1 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active delay (tRRD) Minimum RAS to CAS delay (tRCD) Minimum RAS Pulse Width (tRAS) Module Bank Density Address and Command Setup Time Before Clock Address and Command Hold Time After Clock Data Input Setup Time Before Clock Data Input Hold Time After Clock Reserved SPD Revision Checksum Data Initial 0.9ns 0.9ns 0.5ns 0.5ns 20ns 15ns 20ns 45ns 2/2.5 7ns 0.75ns DDR266A DDR266B -7K 0 1 2 3 4 5 6. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 62 63 -75B 128 256 SDRAM DDR 13 11 1 X72 X72 SSTL 2.5V 7.5ns 0.75ns ECC 7.8us / SR X8 X8 1 Clock 2, 4, 8 4 2/2.5 0 1 Differential Clock, PLL, REGISTER +/-0.2V Voltage Tolerance 7.5ns 0.75ns 10ns 0.75ns N/A N/A 20ns 15ns 20ns 45ns 512MB 0.9ns 0.9ns 0.5ns 0.5ns Undefined Initial Initial 00 A7 1.1ns 1.1ns 0.6ns 0.6ns 90 90 50 50 30ns 15ns 30ns 50ns 50 3C 50 2D 10ns 0.8ns 75 75 2/2.5 0C 8ns 0.8ns 70 75 DDR200 -8B Serial PD Data Entry (Hexadecimal) Note DDR266A DDR266B -7K -75B 80 08 07 0D 0A 01 48 00 04 75 75 02 82 08 08 01 0E 04 0C 01 02 26 00 A0 75 00 00 50 3C 50 2D 40 90 90 50 50 00 00 D7 00 AD B0 B0 60 60 78 3C 78 32 A0 80 0C 80 80 DDR200 -8B
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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NT256D72S89AKGU
256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM
Serial Presence Detect -- Part 2 of 2
32Mx72 1 BANK REGISTERED DDR SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD SPD Entry Value Byte 64-71 72 73-90 91-92 93-94 95-98 1. 2. Description Manufacturer's JEDEC ID Code Module Manufacturing Location Module Part number Module Revision Code Module Manufacturing Data Module Serial Number N/A DDR266A DDR266B -7K -75B NANYA N/A N/A N/A Year/Week Code Serial Number Undefined N/A 00 DDR200 -8B Serial PD Data Entry (Hexadecimal) DDR266A DDR266B -7K -75B 7F7F7F0B00000000 00 00 00 yy/ww 00 00 1, 2 00 DDR200 -8B Note
99-255 Reserved
yy= Binary coded decimal year code, 0-99(Decimal), 00-63(Hex) ww= Binary coded decimal year code, 01-52(Decimal), 01-34(Hex)
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NT256D72S89AKGU
256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM
Absolute Maximum Ratings
Symbol VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT Parameter Voltage on I/O pins relative to Vss Voltage on Input relative to Vss Voltage on VDD supply relative to Vss Voltage on VDDQ supply relative to Vss Operating Temperature (Ambient) Storage Temperature (Plastic) Power Dissipation Short Circuit Output Current Rating -0.5 to VDDQ+0.5 -0.5 to +2.7 -0.5 to +2.7 -0.5 to +2.7 0 to +70 -55 to +150 9 50 Units V V V V C C W mA
Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance
Parameter Input Capacitance: CK0, CK0 Input Capacitance: A0-A12, BA0, BA1, WE, RAS, CAS, CKE0, S0 Input Capacitance: RESET Input Capacitance: SA0-SA2, SCL Input/Output Capacitance DQ0-63; DQS0-8, CB0-7 Input/Output Capacitance: SDA 1. 2. Symbol CI1 CI2 CI3 CI4 CIO1 CIO3 Max. TBD TBD TBD TBD TBD TBD Units pF pF pF pF pF pF Notes 1 1 1 1 1, 2
VDDQ = VDD = 2.5V 0.2V, f = 100 MHz, TA = 25 C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V. DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the board level.
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(c) NANYA TECHNOLOGY CORP.
NT256D72S89AKGU
256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM
DC Electrical Characteristics and Operating Conditions
(TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) Symbol VDD VDDQ VSS, VSSQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) II IOZ IOH IOL 1. 2. 3. 4. Supply Voltage I/O Supply Voltage Supply Voltage, I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (System) Input High (Logic1) Voltage Input Low (Logic0) Voltage Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs Input Leakage Current Any input 0V VIN VDD; (All other pins not under test = 0V) Output Leakage Current (DQs are disabled; 0V Vout VDDQ Output High Current (VOUT = VDDQ -0.373V, min VREF, min VTT) Output Low Current (VOUT = 0.373, max VREF, max VTT) Parameter Min 2.3 2.3 0 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.30 -5 -5 -16.8 16.8 Max 2.7 2.7 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 V DDQ + 0.6 5 5 Units V V V V V V V V V uA uA mA mA 1, 2 1, 3 1 1 1 1, 4 1 1 1 1 Notes 1 1
Inputs are not recognized as valid until VREF stabilizes. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. VID is the magnitude of the difference between the input level on CK and the input level on CK.
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NT256D72S89AKGU
256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Operating, Standby, and Refresh Currents, and Electrical Characteristics and AC Timing.) 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL (AC) and VIH (AC) unless otherwise specified. 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level.
AC Output Load Circuits
VTT 50 ohms Output VOUT 30 pF Timing Reference Point
AC Operating Conditions
(TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) Symbol Parameter/Condition Min V REF + 0.31 0.7 0.5 x VDDQ - 0.2 Max V REF - 0.31 V DDQ + 0.6 0.5 x VDDQ + 0.2 Unit V V V V Notes 1, 2 1, 2 1, 2, 3 1, 2, 4
VIH (AC) Input High (Logic 1) Voltage VIL (AC) Input Low (Logic 0) Voltage VID (AC) Input Differential Voltage, CK and CK Inputs VIX (AC) Input Differential Pair Cross Point Voltage, CK and CK Inputs 1. 2. 3. 4.
Input slew rate = 1V/ ns. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The value of VIX is expected to equal 0.5 x VDDQ of the transmitting device and must track variations in the DC level of the same.
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NT256D72S89AKGU
256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM
Operating, Standby, and Refresh Currents
(TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) Symbol I DD0 Parameter/Condition Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) Auto-Refresh Current: tRC = tRFC (MIN) Self-Refresh Current: CKE 0.2V Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. PC2100 (-7K/-75B) 1500 PC1600 (-8K) 1230 Unit mA Notes 1, 2
I DD1
1730
1410
mA
1, 2
I DD2P I DD2N I DD3P
800 1000 800
650 780 650
mA mA mA
1, 2 1, 2 1, 2
I DD3N
1150
1000
mA
1, 2
I DD4R
2400
1980
mA
1, 2
I DD4W I DD5 I DD6 I DD7 1. 2. 3. 4.
2000 2400 80 3300
1500 2000 80 2880
mA mA mA mA
1, 2 1, 2, 4 1, 2 1, 2
I DD specifications are tested after the device is properly initialized. Input slew rate = 1V/ ns. Enables on-chip refresh and address counters. Current at 7.8 s is time-averaged value of IDD5 at tRFC (MIN) and IDD2P over 7.8 s.
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NT256D72S89AKGU
256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
(TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) (Part 1 of 2) Symbol tAC tDQSCK tCH tCL tCK tCK tDH Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock cycle time CL=2.5 CL=2 -7K Min. -0.75 -0.75 0.45 0.45 7 7.5 0.5 Max. +0.75 +0.75 0.55 0.55 12 12 Min. -0.75 -0.75 0.45 0.45 7.5 10 0.5 -75B Max. +0.75 +0.75 0.55 0.55 12 12 Min. -0.8 -0.8 0.45 0.45 8 10 0.6 -8B Max. +0.8 +0.8 0.55 0.55 12 12 Unit ns ns tCK tCK ns ns ns Notes 1-4 1-4 1-4 1-4 1-4 1-4 1-4, 15, 16 1-4, 15, 16 1-4
DQ and DM input hold time
tDS
DQ and DM input setup time DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK Data-out low-impedance time from CK/CK DQS-DQ skew (DQS & associated DQ signals) DQS-DQ skew (DQS & all DQ signals) Minimum half clk period for any given
0.5
0.5
0.6
ns
tDIPW
1.75
1.75
2
ns
tHZ
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
1-4, 5
tLZ
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
1-4, 5
tDQSQ tDQSQA
0.5 0.5 tCH or tCL tHP 0.75ns 0.75 0.35 0.2 0.2 14 1.25 tCH or tCL tHP 0.75ns 0.75 0.35 0.2 0.2 15
0.5 0.5 tCH or tCL tHP 1.0ns 1.25 0.75 0.35 0.2 0.2 16
0.6 0.6
ns ns
1-4 1-4
tHP
cycle; defined by clk high (tCH ) or clk low (tCL ) time
tCK
1-4
tQH tDQSS tDQSL,H tDSS tDSH tMRD
Data output hold time from DQS Write command to 1st DQS latching transition DQS input low (high) pulse width (write cycle) DQS falling edge to CK setup time (write cycle) DQS falling edge hold time from CK (write cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate)
tCK 1.25 tCK tCK tCK tCK ns
1-4 1-4 1-4 1-4 1-4 1-4
tWPRES tWPST tWPRE tIH
0 0.40 0.25 0.9 0.60
0 0.40 0.25 1.1 0.60
0 0.40 0.25 1.1 0.60
ns tCK tCK ns
1-4, 7 1-4, 6 1-4 2-4, 9, 11, 12 2-4,
tIS
0.9
1.1
1.1
ns
9, 11, 12 2-4,
tIH
1.0
1.1
1.1
ns
10-12, 14
REV 1.1
12/2002
11
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256D72S89AKGU
256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM
AC Timing Specifications for DDR SDRAM Devices Used on Module
(TA = 0 C ~ 70 C; VDDQ = 2.5V 0.2V; VDD = 2.5V 0.2V, See AC Characteristics) (Part 2 of 2) Symbol Parameter Address and control input setup time tIS (slow slewrate) tIPW tRPRE tRPST tRAS tRC command period Auto-refresh to Active/Auto-refresh tRFC command period tRCD tRAP Autoprecharge tRP tRRD command tWR tDAL precharge time tWTR tPDEX tXSNR command tXSRD tREFI Exit self-refresh to read command Average Periodic Refresh Interval 200 7.8 200 7.8 200 7.8 tCK s 1-4 1-4, 8 Internal write to read command delay Power down exit time Exit self-refresh to non-read 75 75 80 ns 1-4 Write recovery time Auto precharge write recovery + 15 (tWR/tCK) + (tRP/tCK) 1 7.5 15 (tWR/tCK) + (tRP/tCK) 1 7.5 15 (tWR/tCK) + (tRP/tCK) 1 8 ns tCK 13 tCK ns 1-4 1-4 1-4 1-4, Precharge command period Active bank A to Active bank B 15 15 15 ns 20 20 20 ns 1-4 1-4 Active to Read or Write delay Active to Read Command with 20 20 20 ns 20 20 20 ns 1-4 1-4 75 75 80 ns 1-4 Input pulse width Read preamble Read postamble Active to Precharge command Active to Active/Auto-refresh 65 65 70 ns 2.2 0.9 0.40 45 1.1 0.60 120,000 2.2 0.9 0.40 45 1.1 0.60 120,000 0.9 0.40 50 1.1 0.60 120,000 ns tCK tCK ns 1.0 1.0 1.1 ns -7K Min. Max. Min. -75B Max. Min. -8B Max. Unit Notes 2-4, 10-12, 14 2-4, 12 1-4 1-4 1-4 1-4
REV 1.1
12/2002
12
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256D72S89AKGU
256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM
AC Timing Specification Notes
1. Input slew rate = 1V/ns. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK is VREF. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from high to low at this time, depending on tDQSS. 8. A maximum of eight Auto refresh commands can be posted to any given DDR SDRAM device. 9. For command/address input slew rate >= 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 10. For command/address input slew rate >= 0.5 V/ns and < 1.0 V/ns. Slew rate is measured between VOH (AC) and VOL (AC). 11. CK/CK slew rates are >= 1.0 V/ns. 12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual system clock cycle time. For example, for PC2100 at CL= 2.5, t DAL = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5. 14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew rate is below 0.5 V/ns. Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns 1. 2. Delta (tIS) 0 +50 +100 Delta (tIH) 0 0 0 Unit ps ps ps Note 1, 2 1, 2 1, 2
Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below 0.5 V/ns. Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns 1. 2. Delta (tDS) 0 +75 +150 Delta (tDH) 0 +75 +150 Unit ps ps ps Note 1, 2 1, 2 1, 2
I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH in the case where DQ, DM, and DQS slew rates differ. Delta Rise and Fall Rate 0.0 ns/V 0.25 ns/V 0.5 ns/V 1. 2. 3. Delta (tDS) 0 +50 +100 Delta (tDH) 0 +50 +100 Unit ps ps ps Note 1-4 1-4 1-4
4.
Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC), similarly for rising transitions. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns. Delta rise, fall = (1/0.5) - (1/0.4) [ns/V] = -0.5 ns/V Using the table above, this would result in an increase in t DS and t DH of 100 ps. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
REV 1.1
12/2002
13
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
NT256D72S89AKGU
256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM
Package Dimensions
FRONT
133.35 5.250 131.35 5.171
128.95 5.077 (2X) 4.00 0.157
Register
10.0 0.394
PLL
2.3 0.091
2.5 0.098
Detail A
Detail B
BACK
3.99 0.157 max. (Front)
17.80 0.700
Register
Detail A 4.00 0.157 3.80 0.15
Detail B 1.00 Width 0.039 1.27 Pitch 0.050
1.27 0.050
1.80 0.071
Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches)
REV 1.1
12/2002
14
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.
4.24 0.167
30.48 1.200
SIDE
NT256D72S89AKGU
256MB : 32M x 72 Low Profile Registered DDR SDRAM DIMM
Revision Log
Rev 0.1 0.2 0.3 1.0 1.1 Date 08/2002 09/2002 09/2002 11/2002 11/2002 12/2002 Preliminary Release Added tPDEX (Power down exit time) to AC Timing Table Updated SPD Table bytes 27, 29, and 63 for DDR200 Updated IDD currents in Operating, Standby, and Refresh Currents Table Official Release Fixed Package Dimensions Modification
REV 1.1
12/2002
15
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
(c) NANYA TECHNOLOGY CORP.

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